1. Field of the Invention
The present invention relates to an apparatus and a method for arbitrating the tight to use a communication link and more particularly to a global bus system.
2. Background of the Related Art
Techniques for arbitrating a global bus system using a round robin method or a packet-bus structure ate known in the art. FIG. 1 illustrates a brief view of a global bus system for arbitrating the use of a communication bus on the basis of a related round robin method. Arbitrating the tight to use the bus through the round robin method is based on assigning a specific period of time within a time division cycle to each processor (node) sharing the global bus. Each processor may access the communication bus periodically, but only during its assigned time slot within the time division cycle. In other words, the method assigns each node to use the bus according to a given sequence and in a given time slot.
In FIG. 1A, there are n nodes (master, slave, . . . ) comprising slave nodes 102 to 105 and a master node 101, which has an arbitration means (algorithm and/or arbitration logic circuit). To arbitrate the right of the n nodes 101 to 105 to use the bus, the bus assert, frame sync and assert clock (clk) signal lines are used. The bus grant (BG), data, clock and reset signals are not needed to perform bus arbitration and, therefore, their description will be omitted. The round robin method allows the master to assign a node the right to use the bus in the given time slot of each TDM cycle. All nodes maintain a count of the active time slot value based on a frame synchronization signal.
Alternatively, a node may access the communication bus for as many time slots as necessary to complete its communication, but may only initiate the communication during its assigned time slot and while the bus is unoccupied by the communication of another node. While the node accessing the bus communicates its information, all other nodes stop counting the passage of time slot periods until the former node finishes using the bus.
FIG. 1B illustrates a timing diagram showing a method for arbitrating the tight to use the bus in the round robin system. There is one counter and the bus assert signal has the same length as the data transfer, because reservation of the bus is not available. Supposing that eleven nodes share the global bus, a first node would have access to the bus in counter periods i, i+11, i+22, etc. The period of time available for transferring and data in each time slot is equal to a stay period of the counter.
FIG. 2 illustrates a method for arbitrating the use of the bus in a pre-arbitration based packet bus system. Here, there are n nodes (master, slave, . . . ) comprising slave nodes 202 to 205 and a master node 201, which has an arbitration means (algorithm and/or arbitration logic circuit). To arbitrate the tight of the n nodes 201 to 205 to use the communication bus, the node address, bus assert request, and sync clk signal lines are used by the master. The bus grant (BG), data, clock and reset signal lines are not needed to perform bus arbitration and, therefore, their description will be omitted. In this configuration, there must be sufficient address lines for the master to individually address all nodes sharing the global bus. For example, if 16 nodes share the bus, then the address bus must have four lines to represent the 4-bit address (24).
To arbitrate the right to use the bus, the master searches all nodes in a fixed sequence and time slot to determine whether there is a bus assert request. If a node requests the use of the bus, the master permits this node to use the bus. While the node assigned to use the bus sends and receives data on the bus, the master continuously searches to determine whether there is another bus request. If another node requests the bus while the bus is actively communicating information, the master reserves the request. When the node actively using the bus finishes communicating, the master permits the next node to use the bus according to the reserved order.
FIG. 2B illustrates a flow chart of a pre-arbitration method employed for a global bus system having eight nodes sharing the communication bus and employing only one bus assertion line. In steps 501 and 502, an initial condition for arbitrating the bus shared by 8 nodes (masters and slaves) is set using one, m=1, bus assert request signal (Bus Assert 0).
Each node has one counter (Count 0 or Count) operating in conjunction with one bus assert line (Bus Assert 0). The bus assert line acts to pause and restart the counter. In this example, the counter (Count 0) is initialized to a value of two to indicate the time slot assigned to node 2.
In step (503), node 2 asserts a bus request (Bus_Req), and a bus grant (BG) is performed by the master in response to the request. Counter 0 within each node receives the bus assert request during the counter period that counter 0 (Counter)contains a value of two, to indicate node 2. When the bus assert request is received, the count of counter 0 within each node is temporarily paused (Count 0=Node 2_Pause).
In step (504), it is determined whether the bus assert of node 2 is finished. If the bus assert of node 2 is not finished, the bus assert request of node 3 waits until bus control of node 2 is finished, using waiting step (505). If the bus assert of node 2 is finished, node 3 is permitted to initiate a bus assert after counter 0 restarts its count.
The related art global bus system of the round robin method shown in FIG. 1A and the packet bus structure capable of pre-arbitration shown in FIG. 2A have the following problems.
In the case of the global bus system of the round robin method, the connection between the nodes is simple. However, because there is only one counter as shown in FIG. 1B, the counter cannot receive and reserve a bus assert request of other nodes, while one node controls bus. Thus, the global bus system is inefficient in arbitrating the use of the bus.
The arbitration method carried out in the packet bus structure, shown in FIG. 2A, can pre-arbitrate. However, because the master requires sufficient address lines to uniquely identify each of the nodes, when a large number of the nodes is used, the connection of the nodes is complicated and a circuit structure for arbitrating the use of bus becomes complex.